ANSYS RedHawk-SC

 

• Golden IR-drop signoff verification for digital designs
• Electromigration reliability signoff
• Timing impact of dynamic voltage drop aggressors
• High-capacity cloud-native infrastructure
• Advanced power analytics and build quality metric
• Foundry certified for all finFET to 3nm

 

ANSYS RedHawk-SC Electrothermal

 

• Comprehensive early prototyping features
• Identifies thermal-mechanical stress
• Integrated with board/system analysis tools
• Power integrity analysis of coupled chip-package system
• RedHawk-SC option for 3D/2.5D chip-package co-analysis
• Thermal simulation

 

ANSYS Totem

 

• Power integrity and noise verification at transistor level
• Capacity for several million xtor flat
• Simultaneous simulation of digital and analog blocks
• Abundant what-if scenarios
• Incremental analysis
• Creates IP power models for use with RedHawk-SC

 

ANSYS PathFinder-SC

 

• Electrostatic discharge (ESD) integrity simulation
• Current density checks
• Layout level and netlist level analysis
• Integrated extraction and simulation engine
• Foundry-certified silicon correlation
• Capacity to analyze full SoCs

 

ANSYS Path FX

 

• Analyzes DvD-aware timing variability
• Critical path timing variability and clock tree analysis
• Single standard cell timing model for any voltages
• SPICE accurate results without voltage interpolation
• High capacity, fast, and SPICE accurate
• Complements STA

 

ANSYS PowerArtist

 

• Analysis-driven power reduction
• Direct links to hardware emulators
• Long vector profiling
• Physically-aware RTL power budgeting
• RTL design-for-power platform

 

ANSYS RaptorH

 

• Electromagnetic on-silicon modeling
• Foundry certified and silicon correlated
• High-capacity and linear multi-CPU scalability
• Includes gold standard HFSS engine
• Models power grids, clock trees, spirals, MiM/MoM caps, etc.
• S-param and RCLk parasitic extraction

 

ANSYS Pharos

 

• Identifies nets susceptible to electromagnetic (EM) crosstalk
• Includes substrate coupling
• Ranks EM aggressors per victim net
• SoC and large block capacity
• What-if capability with point-and-click GUI

 

ANSYS Exalto

 

• Complements digital RC extractors
• Extract entire SoC power grid in minutes
• Highly reduced lumped-element models
• Models electrical, magnetic and substrate coupling
• RLCk signoff extraction tool (post-LVS)
• What-if capability with point-and-click GUI

 

ANSYS VeloceRF

 

• Creates DRC/DFM clean devices
• Generates parameterized PCell/PyCells
• Silicon verified up t0 110GHz
• S-param and compressed RCLk models
• Synthesis and modeling of inductors, transformers and transmission lines